High severity · published May 28, 2024
CVE-2024-30212
Microchip Harmony 3 Core library allows read and write access to RAM via a SCSI READ or WRITE command
7.0
CVSS
0.6%
EPSS
No
On KEV
Description
If a SCSI READ(10) command is initiated via USB using the largest LBA
(0xFFFFFFFF) with it's default block size of 512 and a count of 1,
the first 512 byte of the 0x80000000 memory area is returned to the
user. If the block count is increased, the full RAM can be exposed.
The same method works to write to this memory area. If RAM contains
pointers, those can be - depending on the application - overwritten to
return data from any other offset including Progam and Boot Flash.
Exploitation
Is it being used?
Exploit prediction (EPSS)0.6% · higher than 47% of CVEs
Exploited in the wildNo evidence yet
CISA KEVNot listed
Ransomware campaign useNot known
Affected products
Which versions
MH
MPLAB® Harmony 3 Core Module · Microchip
3.0.0 before 3.13.4 · source: vendor
MH
Mplab Harmony · Microchip
3.0.0 before 3.13.4 · source: CISA
References
NVD
https://nvd.nist.gov/vuln/detail/CVE-2024-30212
CVE.org
https://www.cve.org/CVERecord?id=CVE-2024-30212
github.com
https://github.com/Fehr-GmbH/blackleak
github.com
https://github.com/Microchip-MPLAB-Harmony/core/blob/master/release_notes.md
github.com
https://github.com/Microchip-MPLAB-Harmony/core/commit/d4608a4f1a140bd899cd4337cdbfb343a4339216
